1. Field of Invention
The present invention relates to a low noise amplifier (LNA) circuit, and more particularly, to a differential LNA circuit using integrated CMOS technology for enhanced linearity.
2. Description of the Related Art
In wireless application it is important to constrain power consumption. At the same time, the operating environment often dictates very high performance for the RF front-end. This is particularly accentuated in the case of CDMA systems, because they operate full-duplex (i.e. receiving and transmitting at the same time). It can be shown that, simultaneously with a lower noise figure, the low noise amplifier (LNA) must also have very high IIP3 (input-referred third-order intercept point).
Being a first stage of a wireless receiver, LNA plays a critical role in the entire wireless communication system. As CMOS technology advances, implementation of RF circuits is more and more attractive, such as LNA. In recent years, many CMOS LNAs have been effectively implemented.
Linearity is an important parameter for the LNA, which is one of the main factors dominating the application of CMOS LNA in the wireless systems with high performance requirements. Therefore, a differential LNA circuit with enhanced linearity and improved IIP3 using integrated CMOS technology is desired.